1. Field of the Invention
This invention relates to an interrupt mechanism between two distinct sub-systems using a TDM serial interface. More particularly, it relates to a split-architecture audio codec system for use in a low power mode with an interrupting peripheral device such as a telephone over a telephone line.
2. Background of Related Art
Efficient and inexpensive digitization of telephone grade audio has been accomplished for many years by an integrated device known as a "codec." A codec (short for COder-DECoder) is an integrated circuit or other electronic device which combines the circuits needed to convert analog signals to and from Pulse Code Modulation (PCM) digital signals.
Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo (and even up to 20-bit stereo) for higher quality use beyond that required for telephony. With higher quality audio capability, today's codecs find practical application in consumer stereo equipment including CD players, modems, computers and digital speakers.
With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. One major step toward achieving this high S/N ratio was accomplished more recently by separating the conventional codec into two individual sub-systems and/or two separate integrated circuits (ICs): a controller sub-system handling primarily the digital interface to a host processor, and an analog sub-system handling primarily the interface to, mixing and conversion of analog signals. This split digital/analog architecture has been documented most recently as the "Audio Codec '97 Component Specification", Revision 1.03, Sep. 15, 1996 ("the AC '97 specification"). The AC '97 specification in its entirety is expressly incorporated herein by reference.
As shown in FIG. 3, currently known split-architecture audio codecs contemplate a host processor 400, an audio codec (AC) controller sub-system or IC 402, and an AC analog sub-system or IC 404. The AC analog sub-system 404 comprises some limited amount of digital circuits, but the significant portion of digital control and circuitry is intended to be implemented in the AC controller sub-system 402. The connection between the AC controller sub-system 402 and the AC analog sub-system 404 is currently defined as a five-wire time division multiplexed (TDM) interface controlled by an AC-link 406 in the AC analog sub-system 404. The AC controller sub-system 402 may be a stand alone device, or it may be a portion of a larger device such as a Peripheral Component Interconnect (PCI) interface device. PCI is a processor-independent, self-configuring local bus. Alternatively, the AC controller sub-system 402 may be a part of a central processing unit (CPU).
Because of the capabilities of the split digital/analog architecture (i.e., AC controller sub-system 402 and AC analog sub-system 404), the AC '97 specification includes a significant amount of flexibility intended to capture a large market by satisfying many consumer-related audio needs. For instance, the conventional AC analog sub-system 404 includes interface capability to accept input from multiple sources and to mix the analog signals from those multiple sources in digital form. Possible analog signal sources include a modem or telephone line.
FIG. 4 is a diagram showing relevant features of the conventional AC controller sub-system 402, AC-link 406 and AC analog sub-system 404.
Many consumer devices are powered by battery and enjoy a longer battery life if power can be conserved. To this end, the conventionally known AC controller sub-system 402 and AC analog sub-system 404 include power management support wherein power consumption is greatly reduced by entering a low power mode, sometimes referred to as a halted or sleep mode. In conventional devices the AC controller sub-system 402 places the AC link portion 406 of the AC analog sub-system 404 in a low power mode wherein all clock, sync and data signals are halted by enabling a powerdown register in the command decode section 500 of the AC analog sub-system 404, as shown in FIG. 4.
Unfortunately, the currently known AC controller sub-system 402 and AC analog sub-system 404 provide only two methods for bringing the AC-link 406 and AC analog sub-system 404 out of a low power, halted mode. Regardless of the method, it is the AC controller sub-system 402 that initiates and performs the wake up task.
An external crystal 506 and internal clock circuit 504 provide a 12.288 MHz bit clock signal as one input to AND function 508. A low power enable signal is passed from the command and data portion 520 of the AC controller sub-system 402, over the TDM serial line 550, to set a register in the command decode portion 500 of AC analog sub-system 404. The low power enable signal 560 provides a second input to AND function 508 such that when enabled by the low power enable signal 560, a bit clock signal 554 is provided by the AC analog sub-system 404 to the C controller sub-system 402. When disabled by the low power enable signal 560, the bit clock signal 554 is prevented from clocking the AC controller sub-system 402.
A divide by 256 counter or equivalent function 522 in the AC controller sub-system 402 provides a frame signal after 256 cycles of the bit clock signal 554 to set a frame interrupt register 524.
All communication between the AC controller sub-system 402 and the AC analog sub-system 404 are passed over the two-way TDM bus 550-558, including enable signals to the AC analog sub-system 404. For instance, various registers in the AC analog sub-system 404 may be set by or through the AC controller sub-system 402 to place various components of the AC analog sub-system 404 in a low power, halted or sleep mode. Table I shows the conventional bit assignment of the conventional powerdown register of a split digital/analog architecture audio codec device defined by the AC '97 specification.
TABLE I Powerdown Register BIT FUNCTION PR0 PCM in ADC's & Input Mux Powerdown PR1 PCM out DACs Powerdown PR2 Analog Mixer Powerdown (Vref still on) PR3 Analog Mixer Powerdown (Vref off) PR4 Digital Interface (AC-link) powerdown PR5 Internal clock disable PR6 HP amp powerdown PR7 Modem ADC/DAC off (if supported)
Bit signals PR0 to PR3 and PR5 to PR7 place various components of the AC analog sub-system 404 in the low power, halted or sleep mode. Sequential writes to the powerdown register are performed during normal operation to power down the AC analog sub-system 404 one or more functional blocks at a time. After the desired functional blocks on the AC analog sub-system 404 capable of powerdown are powered down, a final write to bit PR4 places the AC analog sub-system's digital interface, the AC-link 406, in a low-power, halted or sleep mode.
The powerdown register in the command decode section 500 of the AC analog sub-system 404 brings and holds both the bit clock signal 554 and the serial TDM data input 552 provided to the command and data 520 of the AC controller sub-system 402 at a logic low level. The AC controller sub-system 402 thereafter drives the sync line 556 and the serial TDM data out line 550 low after programming the AC-link 406 to the low power, halted, sleep mode.
Once the AC-link 406 has been instructed to halt the bit clock signal 554, i.e., to enter a low power mode, only a special wake up protocol can be used to bring the AC-link 406 back to the active mode since normal audio output and input frames cannot be communicated in the absence of the bit clock signal 554. Once powered down, reactivation of the AC-link 406 is asserted by activation of the sync signal 556 after a minimum of 4 audio frame times following the frame in which the power down was triggered. There are only two conventional methods to bring the AC-link 406 out of the low power, halted, sleep mode: a cold reset, and a warm reset. A cold reset is achieved from the AC controller sub-system 402 by asserting the reset signal 558, which initializes all AC analog sub-system 404 control registers to their default power on reset values. In a warm reset, the AC controller sub-system 402 sends a sync signal 556 to re-activate the AC-link 406 without altering the current AC analog sub-system 404 control register values. The sync signal 556 must be high for a minimum of 0 microsecond in the absence of the bit clock signal 554 to perform the warm reset. To preclude the false detection of a new audio frame and thus a false awakening of the AC analog sub-system 404, the AC-link 406 does not respond to activity on the bit clock signal 554 until the sync signal 556 has been sampled low again.
As shown in FIG. 5A, conventional split architecture audio codecs initially halt operation of the AC analog sub-system 404, then halt operation of the AC controller sub-system 402 as necessary or desired, and ultimately can place the host processor 400 in a low power, halted or sleep mode if desired for maximum power savings. The sequence of waking up the conventional split-architecture audio codec system is typically the opposite of that shown in FIG. 5A, as shown in FIG. 5B, i.e., first the host processor 400 and/or the AC controller sub-system 402 must be operating normally, and lastly the AC analog sub-system 404 is brought to an active mode.
Accordingly, only the AC controller sub-system 402 can wake up the AC analog sub-system 404 once the AC analog sub-system 404 enters the low power mode. Events originated at a peripheral device interfaced only to the AC analog sub-system 404, i.e., analog signal source devices, are not capable of waking up currently known AC controller sub-systems 402. Thus, currently known split-architecture audio codecs cannot allow the AC analog sub-system 404 to enter a low power mode if the system is designed to respond to events originating at a peripheral device. For instance, the conventional AC analog sub-system 404 is not capable of waking up from a low power, halted mode upon detection of an incoming call from a telephone line.